1. Field of the Invention
The present invention relates to a voltage regulator capable of preventing breakdown of an input transistor of an error amplifier circuit when an overshoot occurs at its output.
2. Description of the Related Art
A related-art voltage regulator is now described. FIG. 3 is a circuit diagram illustrating the related-art voltage regulator.
The related-art voltage regulator includes PMOS transistors 104, 105, 106, 109, 111, 114, 115, and 301, NMOS transistors 107, 108, 112, 113, 302, and 303, a reference voltage circuit 110, a constant current circuit 103, resistors 116 and 117, a ground terminal 100, an output terminal 102, and a power supply terminal 101. It is assumed that the size of the PMOS transistor 301 is 0.2 time as large as that of the PMOS transistor 105.
When an overshoot occurs at the output terminal 102, a voltage generated at a gate of the PMOS transistor 111 becomes significantly larger than a reference voltage Vref of the reference voltage circuit 110, which is supplied to a gate of the PMOS transistor 109. When a large overshoot occurs at the output terminal 102, a value of a current flowing through the PMOS transistor 109 usually becomes substantially the same as that of a current of the PMOS transistor 105. A value of a current flowing through the PMOS transistor 111 therefore becomes an extremely small value, which is close to zero. At this time, the NMOS transistor 302 can cause only an extremely small amount of current to flow, and hence the PMOS transistor 301 attempts to cause a current whose value is 0.2 time as large as that of the current of the PMOS transistor 105 to flow.
Then, in turn, a value of a current flowing through the PMOS transistor 301 and the NMOS transistor 302 connected in series becomes extremely small. A drain-source voltage of the PMOS transistor 301 then becomes small, and a voltage at a common connection point of a main current path of the PMOS transistor 301 and the NMOS transistor 302 becomes larger. The NMOS transistor 303 is accordingly brought into an ON state. When the NMOS transistor 303 is brought into the ON state, a current flows from the output terminal 102 toward the ground terminal 100 via the NMOS transistor 303, which exerts an effect of reducing the output voltage as a result (see, for example, FIG. 2 of Japanese Patent Application Laid-open No. 2009-187430).
However, the related-art voltage regulator has a problem in that, when the overshoot occurs at the output terminal 102, a gate voltage of the PMOS transistor 111 also increases accordingly, and hence the gate of the PMOS transistor 111 is broken down.